This invention relates generally to radio-frequency (RF) transmitters and, more particularly to high-speed digital processing techniques used in RF transmitters. As in other applications of electronics, digital signal processing is widely used in communications and specifically in RF transmitters. Because signals in digital form are less prone to inaccuracies than analog signals, it is desirable to maintain signals to be transmitted in the digital domain for as long as possible before converting them to analog form for coupling to an antenna. Most RF transmitters in use today still require one or more states of analog upconversion, in which signals modulating an RF carrier are transformed to equivalent signals modulating an RF carrier of higher frequency. Because analog RF upconversion stages are inherently subject to inaccuracies, there is a need for a digital-to-analog converter that can place the modulated signals at the desired final carrier frequency without using any stages of analog upconversion.
An inherent difficulty in performing direct-to-RF digital-to-analog conversion is that the data rate at the input to the digital-to-analog converter (DAC) must be very high, making it difficult to interface with a standard baseband digital processor, which typically operates at lower frequencies. Therefore, the DAC must be able to accept data at reasonable rates, such as in the low hundreds of megahertz (MHz), but transform these data to a much higher rate for the desired conversion to analog form.
One approach to a direct-to-analog DAC architecture is disclosed in pending patent Application Ser. No. 10/109,834, entitled “Apparatus and Methods for Digital-to-Analog Conversion,” by Jeffrey M. Hinrichs et al., filed Mar. 29, 2002 and published Oct. 2, 2003 as Pub. No. US 2003/0185288 A1. The disclosure of the Hinrichs et al. application is incorporated by reference into this specification.
The prior application of Hinrichs et al. discloses apparatus with an oversampling circuit, a low-speed delta-sigma loop, at least one additional, higher-speed delta-sigma loop, and a high-speed tuning circuit that effects digital upconversion before input to a DAC. The apparatus also includes an upsampling circuit disposed between the first two delta-sigma loops, to increase the data rate of the signal by a process of sample repetition. A delta-sigma modulator loop has the effect of reducing the number of bits of resolution of digital samples applied to it. A delta-sigma loop includes a succession of digital multipliers and adders to perform its function. Necessarily, the earlier multipliers in the loop have to process digital samples of high resolution, which is to say larger digital word lengths. Since processing speed is always an important issue, it is often the speed of the earlier multipliers in a delta-sigma loop that limits the frequency of operation of the overall circuit. In the prior application of Hinrichs et al., delta-sigma modulation and filtering was split into two stages, the first of which was able to operate at a lower speed, to reduce the sample resolution from 18 bits to 13 bits. Following upsampling, the second stage performed further low-pass filtering and reduced the sample resolution from 13 bits to a one-bit resolution for digital-to-analog conversion. While this configuration operates satisfactorily, there is a need for a simpler approach to direct-to-RF digital-to-analog conversion that does not require two stages of delta-sigma modulation. The present invention satisfies this need.